The present invention relates to a PLL (Phase-Locked Loop) circuit for generating a sampling clock, which is phase-locked with color burst, for A/D (Analog/Digital) conversion and a chrominance demodulation circuit by using the PLL circuit. The sampling clock generated by the PLL circuit is used for digitalizing the input composite chrominance signal or chrominance signal.
In a conventional PLL circuit for generating the sampling clock phase-locked with the color burst for A/D conversion, the chrominance sub-carrier is detected during the color burst period; the clock phase-locked with the detected chrominance sub-carrier is generated by controlling the oscillation frequency of VCO (Voltage-Controlled Oscillator); the clock is output, as a sampling clock, to the A/D conversion circuit; the phase of the sampling clock is fine-adjusted by connecting with one another a plurality of delay relays, each delaying by a predetermined amount, in a plurality of stages.
Further, in the conventional way, the chrominance demodulation is made by means of analog demodulation circuit or by digitalizing the analog demodulation circuit.
However, the aforementioned conventional PLL circuit has a problem that the phase of sampling clock is fine-adjusted by connecting a plurality of delay relays, each delaying by a predetermined amount, in a plurality of stages, and so the phase of the sampling clock cannot be varied continuously though it can be fine-adjusted discontinuously.
For instance, the conventional PLL circuit has a problem that it is not suited for accomplishing the demodulation of the color difference signal easily and with a high accuracy.
Further problem of the aforementioned conventional analog demodulation circuit is that such analog circuit picks up the noise intrinsic to the digital circuit when applied to the display such as PDP (Plasma Display Panel) or LCD (Liquid Crystal Display) having digital interface.
Further problem that results from digitalizing a conventional analog demodulation circuit is that the chrominance demodulation and color tone appear somewhat unnatural because of that the phase of the sampling clock for A/D conversion cannot be varied continuously.
For instance, the composite chrominance signal E of NTSC (National TV System Committee) (hereinafter referred to as NTSC signal) is generated by subjecting a chrominance sub-carrier having a frequency of Fsc to 2-phase amplitude quadrature modulation by means of two color difference signals, I and Q, and to frequency multiplication as represented by the following expression.
E=Y+Ixc2x7cos(2xcfx80xc2x7Fscxc2x7t+33xc2x0)+Qxc2x7sin(2xcfx80xc2x7Fscxc2x7t+33xc2x0)xe2x80x83xe2x80x83(1)
where Fsc represents about 3.58 MHz at (455/2) represents horizontal scanning frequency.
The phasic relationship of the chrominance signal, as NTSC signal, is shown in FIG. 1. In FIG. 1, B-Y and R-Y represent two color difference signals differing from I and Q respectively.
The color difference signals, I and Q, have phasic relationships with color burst K as are shown in FIG. 2, so that, where the phase differences from the phase reference point (B-Y axis) are 57xc2x0 and 237xc2x0, the amplitudes are xe2x88x921 and 1 for the color difference signal I and 0 for the color difference signal Q, while, where the phase differences are 147xc2x0 and 327xc2x0, the amplitude of the color difference signal is 0 for the color difference signal I and xe2x88x921 and 1 for the color difference signal Q. (Maximum amplitudes of I and Q are assumed to be 1 and xe2x88x921 respectively.) Thus, I component alone or Q component alone can be sampled by sampling the chrominance signal C (=I+Q) at the point where the amplitude of the color difference signal Q or I becomes 0. In other words, by making the sampling by means of the sampling clock having a frequency of 4 Fsc, which is phase-locked to the aforementioned color burst at 57xc2x0, the color difference signals I and Q can be demodulated from the signal C easily and with a higher accuracy than that available by the estimation based on the interpolating calculation.
However, with the aforementioned PLL circuit, the phase of the sampling clock cannot be varied continuously, thereby causing a problem that the sampling clock having a frequency of 4 Fsc phase-locked to the aforementioned predetermined phase point (e.g., 57xc2x0) of the color burst cannot be generated, and consequently the chrominance signal cannot be demodulated easily and with a high accuracy.
The present invention is made in consideration of the aforesaid problems and for the purpose of providing a PLL circuit capable of continuously varying the phase of the sampling clock for A/D conversion and a chrominance demodulation circuit capable of demodulating color difference signal from a composite video signal with ease and with a high accuracy by using the PLL circuit.
The dual-loop PLL circuit according the present invention comprises a clamping circuit for clamping, for output, the DC level of an input composite chrominance signal or a chrominance signal to a fixed level, an A/D conversion circuit for sampling, for output, the output signal from the clamping circuit, a reference color burst output circuit for comparing, for output, the color burst having a frequency Fsc, out of the output signals from the clamping circuit, with the slice level, a PLL circuit for generating a signal, having a frequency Nxc2x7Fsc (N=an integral number of times of 4) and phase-locked with the reference color burst by means of oscillation frequency control, for output, as a sampling clock, to A/D conversion circuit, and a phase detection circuit for detecting the phase difference between the sampling clock and the reference color burst on the basis of the level difference between the output signal from the A/D conversion circuit and a predetermined phase reference value and for outputting the slice level corresponding to the slice level to the reference color burst output circuit.
Here, the chrominance signal means a signal subjected to carrier-suppression amplitude modulation by means of 2 chrominance signals and 2 chrominance sub-carriers whose phases are differentiated by 90xc2x0 from the formers respectively.
The PLL circuit generates a signal having frequency Nxc2x7Fsc, which is phase-locked with the reference color burst output from the reference color burst output circuit, and outputs the signal, as a sampling clock, to the A/D conversion circuit.
The phase of the color burst output from the reference color burst output circuit is varied at a slice level, while the slice level varies according to the phase reference value in the phase detection circuit. Thus, the sampling clock to be output to the A/D conversion circuit from the PLL circuit is converted into the signal, having frequency NFcs and phase-locked with color burst, and the phase of the signal can be varied continuously according the phase reference value.
For instance, by adjusting the phase at the rising point of the reference color burst so that the phase difference from the phase reference point becomes 57xc2x0, the sampling clock for A/D conversion suited for chrominance demodulation can be output.
The reference color burst output circuit comprises a level comparator for comparing the output signal from the clamping circuit with the slice level to output a signal having a rectangular waveform and a burst period sampling circuit for sampling the signal of color burst period out of the output signals from the level comparator. When arranged in this way, the composition of the reference color burst output circuit can be simplified.
The phase detection circuit comprises an adder for adding a phase adjusting value to phase reference value, a comparator for comparing the sum of the adder with the output signal from the A/D conversion circuit during the period predetermined according to the kind of input signal to output the signal corresponding to the level difference and a slice level output circuit for outputting a corresponding slice level according to the output signal from the comparator.
When arranged in this way, the phase of the sampling clock can be intentionally varied from a predetermined value.
Further, the phase detection circuit comprises the phase reference value selection circuit for selectively output the predetermined reference value for NTSC signal or that for PAL signal, the adder for adding a phase adjusting value to the phase reference value output from the phase reference value selection circuit, the comparator, for comparing the sum of the adder with the output signal of the A/D conversion circuit during the period predetermined depending on whether the signal is of NTSC or PAL and outputting a corresponding signal according to level difference, and the slice level output circuit for outputting a corresponding slice level according to the output signal of the comparator. When arranged in this way, in order to enable_not only the phase of the sampling clock to be intentionally varied from a predetermined value but also to be applicable to the composite chrominance signal or chrominance signal of both the NTSC system and PAL system.
The slice level output circuit is made to comprise a filter for smoothing, for output, the output signal from the comparator and a pulse width modulation circuit for outputting, as slice level, a corresponding pulse width modulation signal on the basis of the output signal of the filter.
When arranged in this way, the composition of the slice level output circuit can be simplified.
A Chrominance Demodulation Circuit Using the Dual-Loop PLL Circuit relating to the invention comprises a clamping circuit for clamping the DC level of input composite chrominance signal or chrominance signal to a fixed level for output, an A/D conversion circuit for sampling the output signal from the clamping circuit by means of sampling clock to output a digital signal, a reference color burst output circuit for comparing the color burst having a frequency Fsc, out of the output signals from the clamping circuit, with the slice level to output a reference color burst having a rectangular waveform, a PLL circuit for generating a signal, having a frequency Nxc2x7Fsc and phase-locked with the reference color burst by means of oscillation frequency control, to output the signal as a sampling clock to the A/D conversion circuit, a phase detection circuit for detecting the phase difference between the sampling clock and the reference color burst on the basis of the level difference between the output signal from the A/D conversion circuit and a predetermined phase reference value, and a signal conversion circuit for converting, for output, the output signal of the A/D conversion circuit into the color difference signal.
The sampling clock to be output from the PLL circuit to the A/D conversion circuit is a signal having a frequency Nxc2x7Fsc and phase-locked with the color burst, and its phase can be adjusted to vary continuously according to phase reference value.
Thus, by setting the phase reference value so that the phase of the sampling lock takes a desired value, the A/D conversion circuit can be made to output the signal C with the color difference signal (e.g., xe2x88x92I, xe2x88x92Q, I, Q) in predetermined sequence. The signal conversion circuit converts the signal C output from the A/D conversion circuit (e.g., xe2x88x92I, xe2x88x92Q, I, Q) into individual color difference signals, I and Q, to be output.
Further, the demodulation being digital demodulation, the noise intrinsic to digital circuit will not occur. Moreover, since the adjustment by continuously varying the phase of the sampling clock is available, unnaturalness will not result from the chrominance demodulation and color tone adjustment.
Also, the signal conversion circuit is made to comprise a multiplier for multiplying, for output, the output signal of the A/D conversion circuit by xe2x88x921 and a selection circuit for selectively outputting the output signal from the A/D conversion circuit and the output signal from the multiplier.
When arranged in this way, the composition of the signal conversion circuit can be simplified.
The reference color burst circuit is made to comprise a level comparator for comparing the output signal of the clamping circuit with the slice level to output a signal having a rectangular waveform and a burst-period sampling circuit for sampling the signal of the color burst period.
When arranged in this way, the composition of the reference color burst output circuit can be simplified.
The phase detection circuit is made to comprise an adder for adding the phase adjusting value for adjusting the color tone to the phase reference value, a comparator for comparing the sum of the adder with the output signal of the A/D conversion circuit during the period predetermined depending on the kind of input signal and a slice level output circuit for outputting a corresponding slice level on the basis of the output signal of the comparator.
This arrangement enables the color tone adjustment. Further, the phase detection circuit comprises the phase reference value selection circuit, for selectively outputting the predetermined phase reference value for NTSC signal or PAL signal by means of selection signal, the adder, for adding the color tone adjusting value to the phase reference value output from the phase reference value selection circuit, the comparator, for comparing the sum of the adder with the output signal from the A/D conversion circuit to output a signal corresponding to the level difference during the period predetermined depending on whether the input signal is of NTSC or of PAL, and the slice level output circuit, for outputting a corresponding slice level according to the output signal from the comparator.
The phase detection circuit arranged in this way not only enables the color tone to be adjusted but also is applicable to both the composite chromiance signal or chrominance signal of NTSC system and PAL (Phase Alternate) system.
The slice level output circuit is made to comprise a filter for smoothing, for output, the output signal of the comparator and a pulse width modulation circuit for outputting a corresponding pulse width modulation signal, as a slice level, on the basis of the output signal of the filter.
When arranged in this way, the composition of the slice level output circuit can be simplified.